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1 ? august 1997 ICM7243 8-character, microprocessor- compatible, led display decoder driver features ? 14-segment and 16-segment fonts with decimal point ? mask programmable for other font-sets up to 64 characters ? microprocessor compatible ? directly drives led common cathode displays ? cascadable without additional hardware ? standby feature turns display off; puts chip in low power mode ? sequential entry or random entry of data into display ? single +5v operation ? character and segment drivers, all mux scan circuitry, 8 x 6 static memory and 64-character ascll font generator included on-chip description the ICM7243 is an 8-character, alphanumeric display driver and controller which provides all the circuitry required to interface a microprocessor or digital system to a 14-segment or 16-segment display. it is primarily intended for use in microprocessor systems, where it minimizes hardware and software overhead. incorporated on-chip are a 64-character ascli decoder, 8 x 6 memory, high power character and segment drivers, and the multiplex scan circuitry. 6-bit ascll data to be displayed is written into the memory directly from the microprocessor data bus. data location depends upon the selection of either sequential (mode = 1) or random access mode (mode = 0). in the sequential access mode the first entry is stored in the lowest location and displayed in the ?left-most? character position. each subsequent entry is automatically stored in the next higher location and displayed to the immediate ?right? of the previous entry. a display full signal is pro- vided after 8 entries; this signal can be used for cascading devices together. a clear pin is provided to clear the mem- ory and reset the location counter. the random access mode allows the processor to select the memory address and display digit for each input word. the character multiplex scan runs whenever data is not being entered. it scans the memory and character drivers, and ensures that the decoding from memory to display is done in the proper sequence. intercharacter blanking is provided to avoid display ghosting. ordering information part number temp. range ( o c) package pkg. no. ICM7243aijl -25 o c to 85 o c 40 ld cerpdip f40.6 ICM7243aipl -25 o c to 85 o c 40 ld pdip e40.6 ICM7243bijl -25 o c to 85 o c 40 ld cerpdip f40.6 ICM7243blpl -25 o c to 85 o c 40 ld pdip e40.6 fn3162.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 pinouts ICM7243a (16-segment character) (pdip, cerdip) top view ICM7243b (14-segment character) (pdip, cerdip) top view 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v dd seg m seg e seg g1 seg k seg c seg d1 seg a1 seg a2 d0 d1 d2 d3 d4 d5 cs wr char 8 char 7 char 6 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 seg l seg g2 seg b seg i seg f seg d2 dp seg h seg j mode a0/sen a1/clr a2/disp full osc/off char 1 char 2 char 3 char 4 v ss char 5 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v dd seg e seg g1 seg k seg c seg d seg a d0 d1 d2 d3 d4 d5 cs cs cs wr char 8 char 7 char 6 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 seg m seg l seg g2 seg b seg i seg f dp seg h seg j mode a0/sen a1/clr a2/disp full osc/off char 1 char 2 char 3 char 4 v ss char 5 ICM7243
3 functional block diagram mode a0/sen a1/clr multiplexer sequential character oscillator data input d0 - d5 d q cl data latches 8 x 6 d1 cl clr d0 adr 6 64 x 17 rom segment drivers segment one shot 8 17 wr cs cs cs mux sel d cl cl d address latches d cl q control cl en clr sequential address counter overflow latch outputs seg x data memory 8 8 character drivers sel 3 address mulitplexer and decoder inter-character blanking character multiplex counter multiplex oscillator osc/off 3 3 a2/disp full char n character outputs (note 1) (note 1) note: 1. ICM7243a has only one cs and no cs . ICM7243b has 15 segments. (note 1) ICM7243
4 absolute maximum ratings thermal information supply voltage v dd - v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0v input voltage (any terminal) . . . . . . . . . . . v dd +0.3v to v ss -0.3v character output current. . . . . . . . . . . . . . . . . . . . . . . . . . . 300ma segment output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -25 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 55 n/a cerdip package . . . . . . . . . . . . . . . . 50 10 maximum junction temperature cerdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 o c pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s). . . . . . . . . . . . . 300 o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indica ted in the operational sections of this specification is not i mplied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical specifications v dd = 5v, v ss = 0v, t a = 25 o c, unless otherwise specified parameter test conditions min typ max units dc characteristics supply voltage (v dd - v ss ), v supp 4.75 5.0 5.25 v operating supply current, i dd v supp = 5.25v, 10 segments on, all 8 characters - 180 - ma quiescent supply current, i stby v supp = 5.25v, osc/off pin < 0.5v, cs = v ss - 30 250 a input high voltage, v ih 2- -v input low voltage, v il --0.8v input current, i in -10 - +10 a character drive current, i char v supp = 5v, v out = 1v 140 190 - ma character leakage current, i chlk - - 100 a segment drive current, i seg v supp = 5v, v out = 2.5v 14 19 - ma segment leakage current, i slk -0.0110 a display full output low, v ol i ol = 1.6ma - - 0.4 v display full output high, v oh l ih = 100 a2.4--v display scan rate, f ds - 400 - hz electrical specifications drive levels 0.4v and 2.4v, timing measured at 0.8v and 2.0v. v dd = 5v, t a = 25 o c, unless otherwise specified parameter test conditions min typ max units ac characteristics wr , clear pulse width low, t wpi 300 250 - ns wr , clear pulse width high (note 1), t wph - 250 - ns data hold time, t dh 0 -100 - ns data setup time, t ds 250 150 - ns address hold time, t ah 125 - - ns address setup time, t as 40 15 - ns cs, cs setup time, t cs 0- -ns pulse transition time, t t - - 100 ns sen setup time, t sen 0-25 - ns display full delay, t wdf 700 480 - ns capacitance parameter test conditions min typ max units input capacitance, c ln (note 2) - 5 - pf output capacitance, c o (note 2) - 5 - pf notes: 1. in sequential mode wr high must be t sen +t wdf . 2. for design reference only, not tested. ICM7243
5 timing waveforms figure 1. random access timing figure 2. sequential access mode timing (mode = 1) figure 3. display characters multiplex timing diagram cs cs address write data valid t cs t ah t as t t t dh t t t wc t wpi t whp t ds valid t wph wr clear sen display full char t sen char char t wdf 12 8 internal char 1 characters drive signals ~ 5 s ~ 300 s inter-character blanking char 2 char 3 char 4 char 5 char 6 char 7 char 8 inter-character blanking signal ICM7243
6 performance curves figure 4. segment current vs output voltage figure 5. character current vs ouput voltage 30 20 10 012 3 i seg (ma) segment voltage (v) v dd = 5.5v 4.5v 5.0v 0 i char (ma) v dd = 5.5v 4.5v 5.0v 012 3 segment voltage (v) 100 200 300 400 500 pin descriptions signal pin function ICM7243a(b) d0 - d5 10 - 15 (8 - 13) six-bit ascll data input pins (active high). cs, cs 16 (14 - 16) chip select from p address decoder, etc. wr 17 write pulse input pin (active low). for an active high write pulse, cs can be used, and wr can be used as cs . mode 31 selects data entry mode. high selects sequential access (sa) mode where first entry is displayed in ?leftmost? character and subsequent entries appear to the ?right?. low selects the random access (ra) mode where data is displayed on t he character addressed via a0 - a2 address pins. a0/sen 30 in ra mode it is the lsb of the character address. in sa mode it is used for cascading devices for displays of more than 8 characters (active high enables device controller). a1/clear 29 in ra mode this is the second bit of the address. in sa mode, a low input will clear the serial address counter, the data memory and the display. a2/display full 28 in ra mode this is the msb of the address. in sa mode, the output goes high after eight entries, indicating display full. osc/off 27 oscillator input pin. adding capacitance to v dd will lower the internal oscillator frequency. an external oscillator can be applied to this pin. a low at this input sets the device into a (shutdown) mode, shutting off the display and oscillator but retaining data stored in memory. seg a - seg m, dp 2 - 9, 32 - 40 (2 - 7), (32 - 40) segment driver outputs. character 1 - 8 18 - 21, 23 - 26 character driver outputs. ICM7243
7 test circuit figure 6. 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v dd seg m seg e seg g1 seg k seg c seg d1 seg a1 seg a2 d0 d1 d2 d3 d4 d5 cs wr char 8 char 7 char 6 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 seg l seg g2 seg b seg i seg f seg d2 dp seg h seg j mode (sa/ra ) a0/sen a1/clr a2/disp full osc/off char 1 char 2 char 3 char 4 char 5 17 segments char 8 segments 8 characters v dd display v dd nc (for sa mode) char 7 char 6 char 5 char 4 char 3 char 2 char 1 segments v dd full output ICM7243a ICM7243
8 typical applications figure 7. driving two rows of characters from a serial input rri drr im6403 uart rbr1 - rbr6 rbr8 rbr7 dr 6 bit bus +5v clr cs sen cs ,wr d0 - d5 cs ICM7243b seg disp full char etc. etc. clr cs sen cs ,wr d0 - d5 cs ICM7243b seg disp full char cs sen cs clr char seg ICM7243b cs disp full d0 - d5 cs sen cs clr char seg ICM7243b cs disp full d0 - d5 wr wr 200pf out v + tr th icl7555 delay 20k +5v +5v +5v 8 characters 8 characters 8 characters 8 characters ICM7243
9 note: 17 for ICM7243a, 15 for ICM7243b. figure 8. multicharacter display using sequential access mode figure 9a. common cathode display figure 9b. common anode display figure 9. driving large displays typical applications (continued) 8-character led display 8 clr +5v sen mode wr d0 - d5 cs char seg disp full v dd v ss data wr , cs, first 8 characters second 8 characters nth 8 characters 8-character led display 8-character led display 88 +5v clr clr sen mode wr d0 - d5 cs char seg disp full v dd v ss clr sen mode wr d0 - d5 cs char seg disp full v dd v ss +5v +5v +5v +5v +5v 6 note 6 note note 6 (cs ) bus (wr) +5v 100 ? 1ma 2n2219 14 ? (100ma peak ) char 14ma 2n6034 1.4a peak gnd r on = 4 ? ICM7243 +5v gnd seg +5v 100 ? 2n2219 (100ma peak ) 1.4a peak gnd r on = 4 ? ICM7243 +5v gnd seg 300 ? gnd +5v 1k 1k 25 ? 1k char 2n6034 ICM7243
10 figure 10. random access 32-character display in a 80c48 system display font and segment assignments figure 11. icm7232a 16-segment character font with decimal point typical applications (continued) cs a2 a1 a0 d0 - d5 wr cs a2 a1 a0 d0 - d5 wr cs a2 a1 a0 d0 - d5 wr cs a2 a1 a0 d0 - d5 wr 80c35 80c48 wr db5 - db0 db6 db7 p22 p21 p20 6 bit bus ICM7243a/b ICM7243a/b ICM7243a/b ICM7243a/b 8 characters 8 characters 8 characters 8 characters 00 01 d5, d4 1 0 11 d30000000011111111 d20000111100001111 d10011001100110011 d00101010101010101 g1 g2 k ml f e b c a1 hj i a2 d2 d1 dp ICM7243
11 detailed description figure 12. ICM7243b 14-segment character font with decimal point figure 13. segment and character drivers output circuit display font and segment assignments (continued) 00 01 d5, d4 1 0 11 d30000000011111111 d20000111100001111 d10011001100110011 d00101010101010101 note: segments a and d appear as 2 segments eac h, but both halves are driven together. g1 g2 k ml f e b c a1 hj i a2 d2 d1 g1 g2 k m f e b c hj i a d1 dp l d v dd segment driver r character driver r ds(on) ~ 4t ? v ss char n segment leds seg x display v led = 1.6v r typical = 100 ICM7243
12 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com w r , cs , cs - these pins are immediately functionally anded, so all actions described as occurring on an edge of wr , with cs and cs enabled, will occur on the equivalent (last) enabling or (first) disabling edge of any of these inputs. the delays from cs pins are slightly (about 5ns) greater than from wr or cs due to the additional inverter required on the former. mode - the mode pin input is latched on the falling edge of wr (or its equivalent, see above). the location (in data memory) where incoming data will be placed is determined either from the address pins or the sequential address counter. this is controlled by mode input. mode also controls the function of a0/sen, a1/clr , and a2/dlsplay full lines. random access mode - when the internal mode latch is set for random access (ra) (mode latched low), the address input on a0, a1 and a2 will be latched by the fall- ing edge of wr (or its equivalent). subsequent changes on the address lines will not affect device operation. this allows use of a multiplexed 6-bit bus controlling both address and data, with timing controlled by wr . sequential access mode - if the internal latch is set for sequential access (sa) , (mode latched high), the serial enable input or sen will be latched on the falling edge of wr (or its equivalent). the clr input is asynchronous, and will force-clear the sequential address counter to address 000 (character 1), and set all data memory contents to 100000 (blank) at any time. the display full output will be active in sa mode to indicate the overflow status of the sequential address counter. if this output is low, and sen is (latched) high, the contents of the counter will be used to establish the data memory location for the data input. the counter is then incremented on the rising edge of wr . if sen is low, or display full is high, no action will occur. this allows easy ?daisy-chaining? of display drivers for mul- tiple character displays in a sequential access mode. changing modes - care must be exercised in any application involving changing from one mode to another. the change will occur only on a falling edge of wr (or its equivalent). when changing mode from sequential access to random access , note that a2/dlsplay full will be an output until wr has fallen low, and an address drive here could cause a conflict. when changing from random access to sequential access , a1/clr should be high to avoid inadvertent clearing of the data memory and sequential address counter. display full will become active immediately after the rising edge of wr. data entry - the input data is latched on the rising edge of wr (or its equivalent) and then stored in the data memory location determined as described above. the six data bits can be multiplexed with the address information on the same lines in random access mode. timing is controlled by the wr input. osc/off - the device includes a relaxation oscillator with an internal capacitor and a nominal frequency of 200khz. by adding external capacitance to v dd at the osc/off pin, this frequency can be reduced as far as desired. alter- natively, an external signal can be injected on this pin. the oscillator (or external) frequency is pre-divided by 64, and then further divided by 8 in the multiplex counter, to drive the character drive lines (see figure 3). an inter-charac- ter blanking signal is derived from the pre-divider. an addi- tional comparator on the osc/off input detects a level lower than the relaxation oscillator's range, and blanks the display, disables the display full output (if active), and clears the pre-divider and multiplex counter. this puts the circuit in a low-power-dissipation mode in which all outputs are effectively open circuits, except for parasitic diodes to the supply lines. thus a display connected to the output may be driven by another circuit (including another ICM7243) without driver conflicts. display output - the output of the multiplex counter is decoded and multiplexed into the address input of the data memory, except during wr operations (in sequential access mode, with sen high and display full low), when it scans through the display data. the address decoder also drives the character outputs, except during the inter-character blanking interval (nominally about 5 s). each character output lasts nominally about 300 s, and is repeated nominally every 2.5ms, i.e., at a 400hz rate (times are based on internal oscillator without external capacitor). the 6 bits read from the data memory are decoded in the rom to the 17 (15 for ICM7243b) segment signals, which drive the segment outputs. both character and seg- ment outputs are disabled during wr operations (with sen high and display full low for sequential access mode). the outputs may also be disabled by pulling osc/off low. the decode pattern from 6 bits to 17 (15) segments is done by a rom pattern according to the ascll font shown. cus- tom decode patterns can be arranged, within these limita- tions, by consultation with the factory. ICM7243

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